As CMOS and other semiconductor technologies shrink in size, there are corresponding improvements in device capacity, bandwidth, and cost. However, shrinking process technologies also present challenges, often requiring designers to compensate for various undesirable side-effects.
As an example, as semiconductor processing technologies have improved, the interconnect traces that semiconductor devices manufacturers use to interconnect components on integrated circuits have become much smaller in both width and depth. Because of this, such traces are often more resistive than in the past. Furthermore, smaller sizes and thinner oxide layers often increase the current leakage of transistor gates. These two factors combine to produce higher voltage drops along device interconnect traces. Such voltage drops can pose problems in many situations, including for example, reduced voltage margins and signal integrity.
The increased density of semiconductor devices also increases the coupling of noise from adjacent traces and device elements.
Compounding these problems is the tendency of many newer devices to utilize lower signal voltages. Voltage drop and noise coupling become even more problematic in the face of such lower absolute and relative voltages.
Various forms of differential signaling are often used to address the problems mentioned above. In one form of differential signaling, often referred to as “pseudo-differential” signaling, a common reference voltage is distributed to multiple signal receivers. Signal voltages are then specified relative to the reference voltage.
To reduce the effects of voltage drop and noise coupling, both a signal and its associated reference voltage are given similar physical routings. Because of their similar routings, both the signal and the reference voltage are subject to similar degrading influences (such as voltage drop and noise coupling), and the signal voltage therefore maintains a generally fixed—or at least proportional—relationship with the reference voltage.
FIG. 1 shows an example of a prior art circuit 10 using pseudo-differential signaling. The circuit has a plurality of signal or data receivers 12, each of which receives one of signals D0 through D3. In addition, a common reference voltage Vref is distributed to each of receivers 12.
In a circuit such as this, the receivers 12 are often arranged in a star or “Kelvin” configuration, in which the traces that distribute Vref to each receiver are approximately the same length. Furthermore, in many implementations the signals D0 through D3 are routed so that they have similar lengths as the traces that conduct Vref, and are therefore subject to similar signal degradations such as noise coupling and voltage drops.
The signals can be digital data signals or analog signals. In either case, the receivers interpret the respective signals D0 through D3 by comparing them to the reference voltage Vref, and in response produce output signals O0-O3.
The techniques illustrated in FIG. 1 are effective to some degree, but can be insufficient in devices where interconnect resistances are high and/or where there are large leakage currents. In FIG. 1, for example, trace resistance is represented by discrete resistor elements R and leakage currents are represented by I. The voltage drop over the length of the Vref traces is equal to the product of I and R. As an example, the traces of a modern CMOS process might exhibit a resistance of 100 milli Ohms per square of trace length. Leakage currents might be on the order of 200 nA per squared micron. Assuming a trace length of 1000 microns and a trace width of 0.33 microns, a typical interconnection scheme might produce a voltage drop of approximately 192 mV between the nominal reference voltage and the actual voltage as it is received by various components.
Such a drop in reference voltage Vref can result in significantly decreased margin or “headroom” between Vref and ground: as Vref approaches ground, there is a smaller and smaller range of voltages that qualify as “low” in comparison to Vref. This has the effect of increasing the sensitivity of the circuit to noise. The problem is particularly acute in high-speed devices where even the nominal or ideal Vref value is relatively low. In devices such as these, any further lowering of Vref threatens to significantly impair device operation. Furthermore, as semiconductor process technologies continue to shrink and operating voltages continue to decrease, voltage drops such as this will become even more significant.